VF
Programme
Internship
Location
Dublin
Duration
10 weeks
About the role
Virtu offers a 10-week FPGA Engineer internship in Dublin, focusing on ultra-low latency trading hardware design. Interns work on real projects with senior mentors, gaining hands-on experience in FPGA and ASIC design lifecycle.
Program Details
- Location: Dublin, Ireland (onsite)
- Duration: 10 weeks, from 2027-06-21 to 2027-08-27
- Ongoing training throughout the summer
- Projects involve real trading and quantitative problems
- Mentorship from senior engineers
- Perks include catered lunches, gym, social events, and laundry service
Role Responsibilities
- Work on FPGA and ASIC hardware design for market-making infrastructure
- Engage in full design lifecycle: architecture, RTL, simulation, verification, and hardware bring-up
- Solve engineering challenges in ultra-low latency trading systems
- Collaborate with experienced engineers and mentors
- Deliver tangible hardware running on silicon by internship end
- No prior finance background required
Requirements
- Academic background in Electrical or Computer Engineering
- Experience with Hardware Description Languages (SystemVerilog, Verilog)
- Familiarity with FPGA vendor tools like Vivado or Quartus
- Comfortable with programming languages such as Python or C++
- Interest in low latency trading systems using FPGAs and ASICs
- Strong problem-solving and communication skills
Application Process
- Initial resume screening
- Online programming test via HackerRank
- Successful candidates contacted for next steps