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Hudson River TradingNew York City, NY

Design Verification (DV) Engineer – 2027 Grads

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Programme

Graduate

Location

New York City, NY

About the role

Design Verification Engineers join HRT’s Hardware team in New York to verify FPGA and ASIC designs supporting low-latency trading. The role focuses on testbenches, verification environments, RTL debugging, continuous integration, and tooling. Candidates need RTL verification experience, Python, Linux familiarity, analytical skills, and a relevant bachelor’s degree.

Responsibilities

  • Create testbenches and tests for hardware platforms using hybrid open-source and proprietary environments.
  • Write detailed verification plans and quickly identify the root causes of RTL bugs.
  • Collaborate with designers to bring up new projects and debug existing designs.
  • Manage test suites and continuous integration infrastructure for hardware verification.
  • Develop and improve open-source and internal verification tools.

Role Context

  • Work within HRT’s Hardware team developing high-performance FPGA and ASIC technologies.
  • Help ensure correctness and robustness of critical hardware in fast-paced, real-time trading environments.
  • No financial experience is necessary for this position.
  • Applicants may apply to only one role; HRT will consider them for all open positions.

Application Information

  • AI tools are prohibited during interviews or assessments unless otherwise instructed or agreed upon.
  • Unauthorized AI assistance may result in disqualification or rescission of an extended offer.