Hardware Engineer Internship – Summer 2027

About the role

This Summer 2027 internship introduces hardware engineering in algorithmic trading. Interns explore FPGA and ASIC design and verification, create SystemVerilog hardware, build Python modeling and testing environments, and work on critical, low-latency infrastructure supporting real-time financial markets.

Responsibilities

• Create hardware using SystemVerilog for FPGA and ASIC design projects.
• Build complex modeling and testing environments in Python for hardware verification.
• Work across low-level computer architecture, logic design, tool writing, and hardware-software interfaces.
• Complete independent projects within HRT’s hardware design and verification environments.
• Learn about HRT’s research, trading infrastructure, and financial markets.

Program Details

• Receive an introduction to the technical facets of hardware engineering in algorithmic trading.
• Explore both FPGA/ASIC Design and Verification roles during the internship.
• Gain exposure to cutting-edge FPGA and ASIC technology.
• Begin project work within the first two weeks after brief training.

Requirements

• Be a full-time student in Computer Engineering, Electrical Engineering, or a related program.
• Graduate and seek full-time roles in 2028.
• Understand digital logic design and/or computer architecture thoroughly.
• Have experience using a hardware design language such as SystemVerilog.
• Have familiarity with C++ and/or Python.
• Know Linux and feel comfortable using its command prompt.

Preferred Qualifications

• Demonstrate a passion for technology and curiosity about how systems work internally.
• Bring exceptional problem-solving skills.
• Have familiarity with FPGAs or ASICs.
• Have exposure to UVM or open-source verification tools such as cocotb.

Application Information

• Apply to one role only; HRT will consider candidates for all open positions during review.
• AI tools are prohibited during interviews or assessments unless explicitly permitted or agreed upon.